/**************************************************************************//**
 * @file     pri_rf.h
 * @version  V1.00
 * $Date: 20/12/14 14:50 $ 
 * @brief    Panchip rf driver header file
 *
 * @note
 * Copyright (C) 2020 Panchip Technology Corp. All rights reserved.
 *****************************************************************************/ 
#ifndef __PAN_PRI_RF_H__
#define __PAN_PRI_RF_H__

#ifdef __cplusplus
extern "C"
{
#endif

#define	PRI_RF_MODE_SEL_TX				(0)
#define	PRI_RF_MODE_SEL_RX				(1)
#define	PRI_RF_MODE_SEL_TRX				(2)

#define	PRI_RF_ADDR_BYTE_LEN_INVALID	(0)
#define	PRI_RF_ADDR_BYTE_LEN_3			(1)
#define	PRI_RF_ADDR_BYTE_LEN_4			(2)
#define	PRI_RF_ADDR_BYTE_LEN_5			(3)

#define	PRI_RF_CHIP_MODE_INVALID		(0)
#define	PRI_RF_CHIP_MODE_BLE			(1)
#define	PRI_RF_CHIP_MODE_297			(2)
#define	PRI_RF_CHIP_MODE_NORDIC			(3)

#define REG_FILE_OFST                       0x0000
#define SEQ_RAM_OFST                        0x1000
#define LIST_RAM_OFST                       0x8000
#define TX_RX_RAM_OFST                      0x8200
#define CTE_IQ_RAM_OFST                     0xB7FC
#define LLHWC_READ32_REG(base_addr, reg_ofst) \
		(*(volatile uint32_t *)((0x50020000) + (base_addr) + (reg_ofst)))
#define LLHWC_WRITE32_REG(base_addr, reg_ofst, data) \
			(*(volatile uint32_t *)(((0x50020000) + (base_addr) + (reg_ofst))) = (data))
#define READ_4_BYTES(pckt, pos) (((uint32_t) (pckt)[pos]) | \
								(((uint32_t) (pckt)[pos + 1]) << 8) | \
								(((uint32_t) (pckt)[pos + 2]) << 16) | \
								(((uint32_t) (pckt)[pos + 3]) << 24))

#define PRI_RF_WRITE_REG_VALUE(base,Reg,Func,Value)     \
        (base->Reg = (base->Reg & ~(Reg##_##Func##_Msk)) | ((Value << Reg##_##Func##_Pos) & Reg##_##Func##_Msk))
#define PRI_RF_READ_REG_VALUE(base,Reg,Func)     \
        ((base->Reg & (Reg##_##Func##_Msk)) >> Reg##_##Func##_Pos)
#define PRI_RF_SET_FUNC_ENABLE(base,Reg,Func,State)     \
		((State == ENABLE) ? (base->Reg |= Reg##_##Func##_Msk) : (base->Reg &= ~Reg##_##Func##_Msk))
/**
  * @brief  This function used to enable or disable auto analysis payload function
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  NewState: new state of enabling state
  * @retval none
  */ 
__STATIC_INLINE void PRI_RF_AutoAnlsPayloadEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,DPY_EN,NewState);
}

/**
  * @brief  This function used to enable or disable crc check function
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  NewState: new state of enabling state
  * @retval none
  */ 
__STATIC_INLINE void PRI_RF_CrcCheckEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,CRC_EN,NewState);
}

/**
  * @brief  This function select crc check mode
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  NewState: new state of crc16 select,if enable,crc16 selected,or crc8 selected
  * @retval none
  */ 
__STATIC_INLINE void PRI_RF_Crc16Select(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,CRC_SEL16,NewState);
}
/**
  * @brief  This function used to enable or disable scamble function
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  NewState: new state of enabling state
  * @retval none
  */ 
__STATIC_INLINE void PRI_RF_ScambleEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,SCR_EN,NewState);
}

/**
  * @brief  This function used to enable or disable enhance mode2(compatible with nordic)
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  NewState: new state of enabling state
  * @retval none
  */ 
__STATIC_INLINE void PRI_RF_NordicEnhanceEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,NORDIC_ENHANCE,NewState);
}

__STATIC_INLINE uint8_t PRI_RF_IsNordicEnhance(PRI_RF_T *rf)
{
	return PRI_RF_READ_REG_VALUE(rf,R00_CTL,NORDIC_ENHANCE);
}
/**
  * @brief  This function used to enable or disable enhance mode
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  NewState: new state of enabling state
  * @retval none
  */ 
__STATIC_INLINE void PRI_RF_EnhanceEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,ENHANCE,NewState);
}

__STATIC_INLINE uint8_t PRI_RF_IsEnhance(PRI_RF_T *rf)
{
    return PRI_RF_READ_REG_VALUE(rf,R00_CTL,ENHANCE);
}
/**
  * @brief  This function used to set band width, 1Mbps or 2Mbps can selected
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  NewState: state of 2Mbps selected,if 1,2Mbps selected, or 1Mbps selected
  * @retval none
  */ 
__STATIC_INLINE void PRI_RF_BandWidth2mSel(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,BW_MODE,NewState);
}

/**
  * @brief  This function used to select chip mode
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  modeSel: chip mode select,including:
  *							PRI_RF_CHIP_MODE_INVALID
  *							PRI_RF_CHIP_MODE_BLE	
  *							PRI_RF_CHIP_MODE_297	
  *							PRI_RF_CHIP_MODE_NORDIC	
  * @retval none
  */ 
__STATIC_INLINE void PRI_RF_ChipModeSel(PRI_RF_T *rf,uint8_t modeSel)	
{
	PRI_RF_WRITE_REG_VALUE(rf,R00_CTL,CHIP_MODE,modeSel);
}

__STATIC_INLINE uint8_t PRI_RF_GetChipMode(PRI_RF_T *rf)	
{
	return PRI_RF_READ_REG_VALUE(rf,R00_CTL,CHIP_MODE);
}

/**
  * @brief  This function used to enable or disable rx ack if rx with payload
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  NewState: new state of enabling state
  * @retval none
  */ 
__STATIC_INLINE void PRI_RF_RxAckEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,RX_ACK_PAYLOAD_EN,NewState);
}

__STATIC_INLINE uint8_t PRI_RF_IsRxAckEn(PRI_RF_T *rf)
{
    return (rf->R00_CTL & R00_CTL_RX_ACK_PAYLOAD_EN_Msk) >> R00_CTL_RX_ACK_PAYLOAD_EN_Pos;
}
/**
  * @brief  This function used to enable or disable tx no ack if function enabled and
  *			tx works in enhance mode,then rx ack is no needed	
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  NewState: new state of enabling state
  * @retval none
  */ 
__STATIC_INLINE void PRI_RF_TxNoAckEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,TX_NOACK_EN,NewState);
}

__STATIC_INLINE uint8_t PRI_RF_IsTxNoAckEn(PRI_RF_T *rf)
{
    return (rf->R00_CTL & R00_CTL_TX_NOACK_EN_Msk) >> R00_CTL_TX_NOACK_EN_Pos;
}

/**
  * @brief  This function used to enable  tx or rx function
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  NewState: new state of function control state,if enabled,rx function enabled,
  * 		or tx function enabled
  * @retval none
  */ 
__STATIC_INLINE void PRI_RF_TrxFuncSel(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,PRI_RX,NewState);
}
__STATIC_INLINE uint8_t PRI_RF_IsRxSel(PRI_RF_T *rf)
{
    return PRI_RF_READ_REG_VALUE(rf,R00_CTL,PRI_RX);
}
/**
  * @brief  This function used to enable or disable all interrupt clear function
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  NewState: new state of enabling state
  * @retval none
  */ 
__STATIC_INLINE void PRI_RF_ClearAllIrqEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R01_INT_CTL,IRQ_CLR_EN,NewState);
}


/**
  * @brief  This function used to set interrupt mask
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  msk: interrupt mask bit,including:
  *						R01_INT_CTL_RX_CRC_ERR_MASK_Msk    
  *						R01_INT_CTL_TX_TIMEOUT_IRQ_MASK_Msk
  *						R01_INT_CTL_TX_IRQ_MASK_Msk        
  *						R01_INT_CTL_RX_IRQ_MASK_Msk        
  * @param  NewState: new state of interrupt mask
  * @retval none
  */
__STATIC_INLINE void PRI_RF_IntMask(PRI_RF_T *rf,uint32_t msk,FunctionalState NewState)
{
    (NewState)?(rf->R01_INT_CTL |= msk):(rf->R01_INT_CTL &= ~msk);
}

/**
  * @brief  This function used to read interrupt flag
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  msk: interrupt flag bit,including:
  *						R01_INT_CTL_RX_CRC_ERR_Msk    
  *						R01_INT_CTL_TX_TIMEOUT_IRQ_Msk
  *						R01_INT_CTL_TX_IRQ_Msk        
  *						R01_INT_CTL_RX_IRQ_Msk        
  * @retval true,interrupt happened
  * @retval false,interrupt does not happened
  */
__STATIC_INLINE bool PRI_RF_IntFlag(PRI_RF_T *rf,uint32_t msk)
{
    return (rf->R01_INT_CTL & msk)?(true):(false);
}

/**
  * @brief  This function used to force exit rx mode
  * @param  rf: where rf is a private rf peripheral base address 
  * @param  NewState: new state of force exit function
  * @retval none
  */
__STATIC_INLINE void PRI_RF_ForceExitRx(PRI_RF_T *rf,FunctionalState NewState)
{
	PRI_RF_SET_FUNC_ENABLE(rf,R01_INT_CTL,EXIT_RX,NewState);
}

/**
  * @brief  This function used to set tx& rx transmit wait time 
  * @param  rf: where rf is a private rf peripheral base address  
  * @param  NewState: new state of enabling state
  * @retval none
  */ 
__STATIC_INLINE void PRI_RF_SetTrxTransWaitTime(PRI_RF_T *rf,uint16_t time)
{
	PRI_RF_WRITE_REG_VALUE(rf,R02_TMR_CTL,TRX_TRANS_WAIT_TIME,time);
}



void PRI_RF_SetTrxPayloadLen(PRI_RF_T *rf,uint8_t mode,uint8_t len);
bool PRI_RF_SetAddrByteLen(PRI_RF_T *rf,uint8_t len);
void PRI_RF_SetPidManualEn(PRI_RF_T *rf,uint8_t pid);
void PRI_RF_SetRxWaitTime(PRI_RF_T *rf,uint16_t time);
void PRI_RF_SetTrxAddr(PRI_RF_T *rf,uint8_t mode,uint32_t *addr);
void PRI_RF_SetTrxRamStartAddr(PRI_RF_T *rf,uint8_t mode,uint32_t addr);
bool PRI_RF_IsTrxRamReady(PRI_RF_T *rf,uint8_t mode);
void PRI_RF_SetTrxRamReady(PRI_RF_T *rf,uint8_t mode,uint8_t ready);
#ifdef __cplusplus
}
#endif

#endif //__PAN_PRI_RF_H__

/*** (C) COPYRIGHT 2016 Panchip Technology Corp. ***/
